Memory speed and bandwidth is almost always of lesser priority than cpu tact frequencies in hpc space. I own several Xeon gold and the epyc 7371 and have run performance benchmarks. My understanding is that Rome plugged into an older board will default to PCIe-3 which satisfies that definition. Does that constitute the entire hpc space? Amd only countered in November last year and even that epic chip performed poorly (7371) vs my other 6146 and 6154 Intel chips in most math computations. As to who in HPC has signed up for rome, take a look at this: L. P., I never claimed that nobody finds utility in this chip for HPC. AMD EPYC delivers on the promise of helping lower TCO and enables organizations to right-size for key datacenter workloads without feature compromise.
EPYC enables up to 6 dedicated GPUs in a single-socket servers with peer-to-peer communication through the CPU. Either workload is CPU bound or it is not. Amd can create as much bandwidth as they like between cpu packages but all that bandwidth is totally wasted with CPUs that clock at around 2.2 – 2.6GHz while Intel is already selling 3.8-4.0+ Xeons that run on such speed for dozens of cores.
In such a topology you don’t need a x16 lane link to connect to other chip/chiplets that also had direct attachement to DDR RAM, as in the previous solutions and topologies of AMD… now the all memory traffic comes from a central location… and the same lane provision in HT or Infinity Fabric, of previous iterations, is sufficient for each Chiplet (previous chips or dies in a socket) to connect to all other 15 chiplets in 2 sockets, if each x16 links can be divided in x4 (they all now only snoop caches in the background and respective very low traffic)… 3 x16 links outside Socket, is 1 x16 for the other central I/O hub, and 8 x4 for the other chiplets-> meaning all chiplets comunicantes with each other even with 2 sockets. But I find the amd hype by fan boys completely over the top.
It is not as if newer features cannot be introduced (AVX123, TSX, etc). @Matthias: “Does that constitute the entire hpc space? So I guess you took issue with my points because you were slightly confused about the definition of HPC and what it encompasses. It may also be that your application is highly tuned over the years for intel’s cache hierarchy (and it’s totally reasonable to go with intel at that point).Hft is definitely part of HPC, regardless of how you or I feel about it.
While all of our previous material focused on 128x PCIe lanes, in single and dual socket configurations for AMD EPYC, we are expecting a big change in 2019 with the new generations and one that Intel fully failed to address with its release this week. I can’t speak for Rome as they are not out yet but I am prepared to be disappointed. This board comes with the ultimate in connectivy: AMD's EPYC 7002-series chips deliver an impressive 128 high-speed PCIe 4.0 lanes, and ASRock Rack is keen to take advantage of them.
Epyc is a brand of x86-64 microprocessors designed and sold by AMD, based on the company's Zen microarchitecture. Cascade’s been out hours and already looks like a dinosaur.Only one thing left to wonder about, how fast is the connection between the chiplets and the I/O die? All AMD is doing is removing the past bottleneck but they still hugely under perform Xeons. The current generation managed to get a product shipped, but it did something more. Epyc 7371 benchmarks vs Intel CPUs are in public domain, check them out (specifically vector compute) .
I acknowledged the areas I have zero expertise in, but claim to know a thing or two about what I have been doing over the past 11 years. Can? Linpack? When I discuss the AMD EPYC 7001 series Infinity Fabric link between sockets, I usually tell people to conceptually think of it as a PCIe Gen3 x16 link between dies plus a little bit of extra juice. And AMD sales was quoted in interviews with Anand tech.
Let’s agree to disagree at this point and if I hurt your feelings with “zero applicability” then I apologize and happily correct it to “currently low applicability”@Matthias You do realize that your purported conclusion is actually contradicted by your cited reference?The logic behind the article is big data and hpc influencing high frequency trading. The article you quoted does not go into any detail on the precise use case where the Rome chips are supposed to be utilized. Intel- based Supermicro SYS-1029U-TRTP server scored 94 in tests conducted in AMD labs configured with 2 x Xeon 5118 CPU’s, 768GB memory (24*32GB 2R DDR4 2666MHz running at 2400MHz), SLES 12 SP3 4.4.92-6.18-default kernel, BIOS set to Extreme performance setting. If Rome will solve your problem then by all means go for it. Patrick is a consultant in the technology industry and has worked with numerous large hardware and storage vendors in the Silicon Valley. The article furthermore treats all three areas as separate entities hence leading your conclusion ad absurdum.
If you really needed lots of memory channels and memory in addition to lots of cores, 1P is probably not for you. In a single socket AMD EPYC 7001 server, this gives us 128x PCIe Gen3 lanes. Multiply cores by 2 as those are being deployed on dual socket boards and you get your dozens.
AMD EPYC provides up to 32 cores, 8 memory channels and 128 PCIe® 3.0 lanes per CPU unlocking capabilities and performance previously available only in 2-socket architectures.
Patrick has been running STH since 2009 and covers a wide variety of SME, SMB, and SOHO IT topics. And if you still disagree then, we’ll, let’s agree to disagree.
For sure. I pointed to the sources, feel free to look it up.
Hence the I/O.
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